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? semiconductor components industries, llc, 2012 february, 2012 ? rev. 3 1 publication order number: ncp3155/d ncp3155a, ncp3155b 3 a synchronous buck regulator the ncp3155 is a dc/dc synchronous switching regulator with fully integrated power switches and full fault protection. the switching frequency of 1 mhz and 500 khz allows the use of small filter components, which results in smaller board space and reduced bom cost. available in a soic-8 package. features ? input voltage range from 4.7 v to 24 v ? adjustable output voltage ? 1 mhz operation (ncp3155a ? 500 khz) ? internally programmed 1.2 ms soft ? start (ncp3155a ? 2.4 ms) ? 0.8 1.0% reference voltage ? 48 m hs ? fet and 18 m ls ? fet ? current limit protection ? transconductance amplifier with external compensation ? input undervoltage lockout ? output overvoltage and undervoltage detection ? these are pb ? free devices typical applications ? set top boxes ? dvd drives and hdd ? lcd monitors and tvs ? cable modems ? telecom/networking/datacom equipment figure 1. typical application circuit ncp3155 fb1 4.7 v ? 24 v bst vsw pgnd agnd iset comp v in v out http://onsemi.com soic ? 8 nb case 751 marking diagram 3155x alyw 1 8 1 8 pin connections fb comp agnd bst iset v in v sw pgnd (top view) device package shipping ? ordering information NCP3155ADR2G soic ? 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. ncp3155bdr2g soic ? 8 (pb ? free) 2500 / tape & reel 3155x = specific device code x = a or b a = assembly location l = wafer lot y = year w = work week = pb ? free package
ncp3155a, ncp3155b http://onsemi.com 2 gate drive logic vc clk/ dmax/ soft start oov boost active level shift sample & hold vc hsdrv pgnd agnd ? + ? + ? + vin comp fb ref ramp oscillator bst vsw vin figure 2. ncp3155 block diagram internal bias iset 1.5 v thermal sd por/startup ouv current limit vin iset lsdrv pin function description pin pin name description 1 pgnd the pgnd pin is the high current ground pin for the lower mosfet and drivers which should be soldered to a large copper area to reduce thermal resistance. 2 v in the v in pin powers the internal control circuitry and is monitored by an undervoltage comparator. the v in pin is also connected to the internal power nmos switch. it is also used in conjunction with the v sw pin to sense current in the high side mosfet. the v in pin has high di/dt edges and must be decoupled to pgnd pin close to the pin of the device. 3 bst supply rail for the floating top gate driver. connect a capacitor (cbst) between this pin and the v sw pin. typ- ical values for cbst range from 1 nf to 100 nf. 4 comp compensation pin. the comp pin is the output of the transconductance amplifier and the non ? inverting input of the pwm comparator. the comp pin in conjunction with the fb pin are used to compensate the voltage ? control feedback loop. 5 fb inverting input to the operational transconductance amplifier (ota). the fb pin in conjunction with the extern- al compensation serves to stabilize and achieve the desired output voltage with voltage mode compensation. 6 agnd the agnd pin serves as small ? signal ground. all small ? signal ground paths should connect to the agnd pin at a single point to avoid any high current ground returns. 7 iset bottom gate mosfet driver pin and the internal current set pin. place a resistor to ground to set the current limit of the converter. 8 v sw the v sw pin is the connection of the drain and source of the internal n mosfets. the v sw pin swings from v in when the high side switch is on to small negative voltages when the low side switch is on with high dv/dt transitions.
ncp3155a, ncp3155b http://onsemi.com 3 absolute maximum ratings (measured vs. gnd pin 8, unless otherwise noted) rating symbol v max v min unit main supply voltage input v cc 26.4 ? 0.3 v boost to v sw differential voltage bst ? v sw 13.2 ? 0.3 v high side drive boost pin bst 45 ? 0.3 v switch voltage node v sw 30 ? 0.6 v transconductance amplifier output comp 5.5 ? 0.3 v feedback fb 6.0 ? 0.3 v current limit set iset 13.2 ? 0.3 v operating junction temperature range (note 1) t j ? 40 to +125 c maximum junction temperature t j(max) +150 c storage temperature range t stg ? 55 to +150 c thermal characteristics ? soic ? 8 package (note 2) thermal resistance junction ? to ? air (note 3) r ja 110 170 c/w lead temperature soldering (10 sec): reflow (smd styles only) pb ? free (note 3) r f 260 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja 2. the value of ja is measured with the device mounted on 1 in 2 fr 4 board with 1 oz. copper, in a still air environment with t a = 25 c. the value in any given application depends on the user?s specific board design. 3. the value of ja is measured with the device mounted on minimum footprint, in a still air environment with t a = 25 c. the value in any given application depends on the user?s specific board design.
ncp3155a, ncp3155b http://onsemi.com 4 electrical characteristics ( ? 40 c < t j < +125 c, v cc = 12 v, for min/max values unless otherwise noted) characteristic conditions min typ max unit input voltage range ? 4.7 24 v supply current v cc supply current ncp3155a v fb = 0.8 v, switching, v cc = 4.7 v ? 11.1 ? ma v fb = 0.8 v, switching, v cc = 24 v ? 31.5 ? ma v cc supply current ncp3155b v fb = 0.8 v, switching, v cc = 4.7 v ? 16.5 ? ma v fb = 0.8 v, switching, v cc = 24 v ? 54.7 ? ma under voltage lockout uvlo rising threshold v cc rising edge 4.0 4.3 4.7 v uvlo falling threshold v cc falling edge 3.5 3.9 4.3 v oscillator oscillator frequency ncp3155a t j = +25 c, 4.7 v v cc 24 v 415 500 585 khz t j = ? 40 c to +125 c, 4.7 v v cc 24 v 400 500 600 khz oscillator frequency ncp3155b t j = +25 c, 4.7 v v cc 24 v 830 1000 1170 khz t j = ? 40 c to +125 c, 4.7 v v cc 24 v 820 1000 1180 khz ramp ? amplitude voltage v peak ? v alley ? 1.5 ? v ramp valley voltage 0.46 0.71 0.85 v pwm minimum duty cycle (note 4) ? 7.0 ? % maximum duty cycle 80 84 ? % soft start ramp time ncp3155a ncp3155b v fb = v comp ? ? 2.4 1.2 ? ? ms error amplifier (gm) transconductance 0.9 1.3 1.9 ms open loop dc gain (notes 4 and 6) ? 70 ? db output source current v fb = 750 mv 45 70 100 a output sink current v fb = 850 mv 45 70 100 a fb input bias current ? 0.5 500 na feedback voltage tj = 25 c 4.7 v < v in < 24 v, ? 40 c < t j < +125 c 0.792 0.784 0.8 0.8 0.808 0.816 v v comp high voltage v fb = 750 mv 4.0 4.4 5.0 v comp low voltage v fb = 850 mv ? 72 250 mv output voltage faults feedback oov threshold 0.91 1.00 1.09 v feedback ouv threshold 0.56 0.60 0.64 v pwm output stage high ? side switch on resistance v in = 12 v v in = 4.7 v ? ? 48 65 63 85 m low ? side switch on resistance v in = 12 v v in = 4.7 v ? ? 18 21 35 50 m overcurrent iset source current 7 13.5 18 a current limit set voltage (note 5) r set = 22.1 k ? 298 ? mv thermal shutdown thermal shutdown (notes 4 and 7) ? 175 ? c hysteresis (notes 4 and 7) ? 20 ? c 4. guaranteed by design. 5. the voltage sensed across the high side mosfet during conduction. 6. this assumes 100 pf capacitance to ground on the comp pin and a typical internal r o of > 10 m . 7. this is not a protection feature.
ncp3155a, ncp3155b http://onsemi.com 5 typical performance characteristics 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 efficency (%) i out , output current (a) figure 3. efficiency vs output current and output voltage v out = 5.0 v 3.3 v 1.5 v 1.2 v ncp3155a, v in = 12 v typical application circuit figure 45 figure 4. efficiency vs output current and output voltage 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 i out , output current (a) efficency (%) ncp3155b, v in = 12 v typical application circuit figure 45 v out = 5.0 v 3.3 v 1.5 v 1.2 v figure 5. efficiency vs output current and input voltage efficency (%) i out , output current (a) 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 ncp3155a, v out = 5 v typical application circuit figure 45 v in = 12 v v in = 24 v v in = 18 v 4.96 4.98 5 5.02 5.04 5.06 5.08 5.1 4.9 4.92 4.94 4.96 4.98 5 5.02 5.04 5.06 5.08 5.1 v out (v) figure 6. load regulation vs input voltage i out , output current (a) ncp3155a, v out = 5 v typical application circuit figure 45 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 v in = 24 v v in = 12 v v in = 18 v input = 12 v, output = 5.0 v, load = 2 a, ch3 (purple) = v in , (ch2) green = v out , ch1 (yellow) = vsw ch3: 200 mvac/div; ch2: 50 mvac/div; ch1: 5.0 v/div time scale: 2.0 s/div; figure 45 figure 7. switching waveforms (ncp3155a) input = 18 v, output = 5.0 v, load = 2 a, ch3 (purple) = v in , (ch2) green = v out , ch1 (yellow) = vsw ch3: 200 mvac/div; ch2: 50 mvac/div; ch1: 5.0 v/div time scale: 2.0 s/div; figure 45 figure 8. switching waveforms (ncp3155a)
ncp3155a, ncp3155b http://onsemi.com 6 typical performance characteristics input = 12 v, output = 1.8 v, load = 2 a, ch3 (purple) = v in , (ch2) green = v out , ch1 (yellow) = vsw ch3: 200 mvac/div; ch2: 50 mvac/div; ch1: 5.0 v/div time scale: 1.0 s/div; figure 46 figure 9. switching waveforms (ncp3155b) 792 794 796 798 800 802 804 806 808 ? 40 ? 25 ? 105 203550658095110125 v fb (mv) temperature ( c) figure 10. feedback reference voltage vs temperature 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 f sw (khz) temperature ( c) figure 11. switching frequency vs input voltage and temperature v in = 12 v ? 24 v v in = 4.7 v 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1100 1120 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 f sw (khz) temperature ( c) figure 12. switching frequency vs input voltage and temperature ncp3155a ncp3155b v in = 12 v ? 24 v v in = 4.7 v 1.3 1.32 1.34 1.36 1.38 1.4 1.42 1.44 1.46 1.48 1.5 ? 40 ? 25 ? 105 203550658095110125 g m (ms) temperature ( c) figure 13. transconductance vs temperature 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 40 25 10 5 20 35 50 65 80 95 110 125 temperature ( c) figure 14. input undervoltage vs temperature uvlo (v) uvlo rising uvlo falling
ncp3155a, ncp3155b http://onsemi.com 7 typical performance characteristics 400 500 600 700 800 900 1000 1100 1200 ? 40 ? 25 ? 105 203550658095110125 temperature ( c) figure 15. output protection vs temperature threshold voltage (mv) output overvoltage threshold output undervoltage threshold 400 450 500 550 600 650 700 750 800 850 900 950 1000 ? 40 ? 25 ? 105 203550658095110125 temperature ( c) figure 16. ramp valley voltage vs temperature valley voltage (mv) 10 11 12 13 14 15 16 17 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 temperature ( c) figure 17. iset current vs temperature iset ( a) input = 12 v, output = 1.8 v, load = 2 a, ch3 (purple) = v in , (ch2) green = v out , ch1 (yellow) = vsw ch3: 10 v/div; ch2: 2.0 v/div; ch1: 5.0 v/div time scale: 1.0 ms/div; figure 45 figure 18. startup waveforms (ncp3155a) input = 12 v, output = 1.8 v, load = 2 a, ch3 (purple) = v in , (ch2) green = v out , ch1 (yellow) = vsw ch3: 10 v/div; ch2: 1.0 v/div; ch1: 5.0 v/div time scale: 0.5 ms/div; figure 46 figure 19. startup waveforms (ncp3155b) input = 12 v (ch2) green = v out , ch1 (yellow) = vsw ch2: 0.5 v/div; ch1: 5.0 v/div time scale: 2.0 ms/div; figure 45 figure 20. current limit waveforms (ncp3155a)
ncp3155a, ncp3155b http://onsemi.com 8 typical performance characteristics input = 12 v (ch2) green = v out , ch1 (yellow) = vsw ch2: 0.5 v/div; ch1: 5.0 v/div time scale: 2.0 ms/div; figure 46 figure 21. current limit waveforms (ncp3155b) 0 10 20 30 40 50 60 70 80 90 100 110 40 25 10 5 20 35 50 65 80 95 110 125 r ds(on) (m ) temperature ( c) figure 22. high ? side mosfet r ds(on) vs temperature v in = 10 v ? 24 v v in = 5.0 v 0 5 10 15 20 25 30 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 r ds(on) (m ) temperature ( c) figure 23. low ? side mosfet r ds(on) vs temperature v in = 10 v ? 24 v v in = 5.0 v 0 0.5 1 1.5 2 2.5 3 3.5 25 30 35 40 45 50 55 60 65 70 75 80 85 1.0 v < v out < 1.8 v 3.3 v 2.5 v output current (a) t a , ambient temperature ( c) figure 24. derating curve, 12 v input 0 0.5 1 1.5 2 2.5 3 3.5 25 30 35 40 45 50 55 60 65 70 75 80 85 output curreent (a) t a , ambient temperature ( c) figure 25. derating curve, 18 v input v out = 5.0 v 1.8 v 3.3 v 2.5 v 0 0.5 1 1.5 2 2.5 3 3.5 25 30 35 40 45 50 55 60 65 70 75 80 85 output current (a) t a , ambient temperature ( c) figure 26. derating curve, 24 v input 3.3 v v out = 5.0 v 12 v 2.5 v v out = 5.0 v ncp3155a ncp3155a ncp3155a
ncp3155a, ncp3155b http://onsemi.com 9 typical performance characteristics 0 0.5 1 1.5 2 2.5 3 3.5 25 30 35 40 45 50 55 60 65 70 75 80 85 output current (a) t a , ambient temperature ( c) figure 27. derating curve, 12 v input 3.3 v v out = 5.0 v 1.0 to 1.2 v 2.5 v 1.8 v 0 0.5 1 1.5 2 2.5 3 3.5 25 30 35 40 45 50 55 60 65 70 75 80 85 v out = 5.0 v 3.3 v 2.5 v 1.8 v t a , ambient temperature ( c) figure 28. derating curve, 18 v input output current (a) figure 29. derating curve, 24 v input 0 0.5 1 1.5 2 2.5 3 3.5 25 30 35 40 45 50 55 60 65 70 75 80 85 t a , ambient temperature ( c) output current (a) v out = 5.0 v 2.5 v 3.3 v 12 v ncp3155b ncp3155b ncp3155b
ncp3155a, ncp3155b http://onsemi.com 10 detailed description overview the ncp3155a/b operates as a 500 khz/1.0 mhz, voltage mode, pulse width modulated, (pwm) synchronous buck converter. it drives high ? side and low ? side n ? channel power mosfets. the ncp3155 incorporates an internal boost circuit consisting of a boost clamp and boost diode to provide supply voltage for the high side mosfet gate driver. the ncp3155 also integrates several protection features including input undervoltage lockout (uvlo), output undervoltage (ouv), output overvoltage (oov), adjustable high ? side current limit (i set and i lim ), and thermal shutdown (tsd). the operational transconductance amplifier (ota) provides a high gain error signal from vout which is compared to the internal 1.5 v pk-pk ramp signal to set the duty cycle converter using the pwm comparator. the high side switch is turned on by the positive edge of the clock cycle going into the pwm comparator and flip flop following a non-overlap time. the high side switch is turned off when the pwm comparator output is tripped by the modulator ramp signal reaching a threshold level established by the error amplifier. the gate driver stage incorporates fixed non ? overlap time between the high ? side and low ? side mosfet gate drives to prevent cross conduction of the power mosfet?s. por and uvlo the device contains an internal power on reset (por) and input undervoltage lockout (uvlo) that inhibits the internal logic and the output stage from operating until v cc reaches its respective predefined voltage levels (4.3 v typical). startup and shutdown once v cc crosses the uvlo rising threshold the device begins its startup process. closed ? loop soft ? start begins after a 400 s delay wherein the boost capacitor is charged, and the current limit threshold is set. during the 400 s delay the ota output is set to just below the valley voltage of the internal ramp. this is done to reduce delays and to ensure a consistent pre ? soft ? start condition. the device increases the internal reference from 0 v to 0.8 v in 32 discrete steps while maintaining closed loop regulation at each step. each step contains 32 switching cycles. some overshoot may be evident at the start of each step depending on the voltage loop phase margin and bandwidth. the total soft ? start time is 2.4 ms for the ncp3155a and 1.2 ms for the ncp3155b. figure 30. soft ? start details internal reference voltage 25 mv steps 0.8 v 0v 0 .7v ota output internal ramp output voltage 32 voltage steps
ncp3155a, ncp3155b http://onsemi.com 11 oov and ouv the output voltage of the buck converter is monitored at the feedback pin of the output power stage. two comparators are placed on the feedback node of the ota to monitor the operating window of the feedback voltage as shown in figures 31 and 32. all comparator outputs are ignored during the soft ? start sequence as soft ? start is regulated by the ota and false trips would be generated. after the soft ? start period has ended, if the feedback is below the reference voltage of comparator 2 (v fb < 0.6 v), the output is considered ?undervoltage? and the device will initiate a restart. when the feedback pin voltage rises between the reference voltages of comparator 1 and comparator 2 (0.6 < v fb < 1.0), then the output voltage is considered ?power good.? finally, if the feedback voltage is greater than comparator 1 (v fb > 1.0 v), the output voltage is considered ?overvoltage,? and the device will latch off. to clear a latch fault, input voltage must be recycled. graphical representation of the oov and ouv is shown in figures 33 and 34. vref = 0.8 v vref*75% vref*125% comparator 1 comparator 2 logic soft start complete restart latch off fb figure 31. oov and ouv circuit diagram power good = 1 power good = 1 vref = 0.8 v voov = vref * 125% ouvp & power good = 0 oovp & power good = 0 hysteresis = 5 mv hysteresis = 5 mv power not good high power not good low figure 32. oov and ouv window diagram vouv = vref * 75%
ncp3155a, ncp3155b http://onsemi.com 12 0.8 v (vref *100%) 0.6 v (vref *75%) 1.0 v (vref *125%) fb voltage latch off reinitiate softstart softstart complete figure 33. powerup sequence and overvoltage latch 0.8 v (vref *100%) 0.6 v (vref * 75%) 1.0 v (vref *125%) fb voltage latch off reinitiate softstart softstart complete figure 34. powerup sequence and undervoltage soft ? start
ncp3155a, ncp3155b http://onsemi.com 13 current limit and current limit set overview the ncp3155 uses the voltage drop across the high side mosfet during the on time to sense inductor current. the i limit block consists of a voltage comparator circuit which compares the dif ferential voltage across the v cc pin and the v sw pin with a resistor settable voltage reference. the sense portion of the circuit is only active while the hs mosfet is turned on. control vset 6 rset iset 13 ua dac / counter ilim out pgnd iset vsw vin vcc itrip ref vsense switch cap figure 35. i set / i limit block diagram itrip ref ? 63 steps, 6.51 mv/step current limit set the i limit comparator reference is set during the startup sequence by forcing a typically 13 a current through the low side gate drive resistor. the gate drive output will rise to a voltage level shown in the equation below: v set i set *r set (eq. 1) where i set is 13 a and r set is the gate to source resistor on the low side mosfet. this resistor is normally installed to prevent mosfet leakage from causing unwanted turn on of the low side mosfet. in this case, the resistor is also used to set the i limit trip level reference through the i limit dac. the i set process takes approximately 350 s to complete prior to soft ? start stepping. the scaled voltage level across the i set resistor is converted to a 6 bit digital value and stored as the trip value. the binary i limit value is scaled and converted to the analog i limit reference voltage through a dac counter. the dac has 63 steps in 6.51 mv increments equating to a maximum sense voltage of 403 mv. during the i set period prior to soft ? start, the dac counter increments the reference on the i set comparator until it crosses the v set voltage and holds the dac reference output to that count value. this voltage is translated to the i limit comparator during the i sense portion of the switching cycle through the switch cap circuit. see figure 35. exceeding the maximum sense voltage results in no current limit. steps 0 to 10 result in an effective current limit of 0 mv. current sense cycle figure 36 shows how the current is sampled as it relates to the switching cycle. current level 1 in figure 36 represents a condition that will not cause a fault. current level 2 represents a condition that will cause a fault. the sense circuit is allowed to operate below the 3/4 point of a given switching cycle. a given switching cycle?s 3/4 t on time is defined by the prior cycle?s t on and is quantized in 10 ns steps. a fault occurs if the sensed mosfet voltage exceeds the dac reference within the 3/4 time window of the switching cycle.
ncp3155a, ncp3155b http://onsemi.com 14 1/4 1/2 to n ? 1 1/4 3/4 to n ? to n ? 2 ? to n ? 1 no trip: vsense < i trip ref at 3/4 point trip: vsense > i trip ref at 3/4 point 3/4 3/4 point determined by prior cycle vsense 1/2 current level 2 current level 1 itrip ref figure 36. i limit trip point description each switching cycle?s ton is counted in 10 ns time steps. the 3/4 sample time value is held and used for the following cycle?s limit sample time soft ? start current limit during soft ? start the i set value is doubled to allow for inrush current to charge the output capacitance. the dac reference is set back to its normal value after soft ? start has completed. v sw ringing the i limit block can lose accuracy if there is excessive v sw voltage ringing that extends beyond the 1/2 point of the high ? side transistor on ? time. proper snubber design and keeping the ratio of ripple current and load current in the 10 ? 30% range can help alleviate this as well. current limit a current limit trip results in completion of one switching cycle and subsequently half of another cycle t on to account for negative inductor current that might have caused negative potentials on the output. subsequently the power mosfets are both turned off and a 4 soft ? start time period wait passes before another soft ? start cycle is attempted. i ave vs trip point the average load trip current versus r set value is shown the equation below: i avetrip i set r set r ds(on) 1 4 v in v out l v out v in 1 f sw (eq. 2) where: l = inductance (h) i set = 13 a r set = gate to source resistance ( ) r ds(on) = on resistance of the hs mosfet (48 m ) v in = input voltage (v) v out = output voltage (v) f sw = switching frequency (hz) boost clamp functionality the boost circuit requires an external capacitor connected between the bst and v sw pins to store char ge for supplying the high and low ? side gate driver voltage. this clamp circuit limits the driver voltage to typically 7.5 v when v in > 9 v, otherwise this internal regulator is in dropout and typically v in ? 1.25 v. the boost circuit regulates the gate driver output voltage and acts as a switching diode. a simplified diagram of the boost circuit is shown in figure 37. while the switch node is grounded, the sampling circuit samples the voltage at the boost pin, and regulates the boost capacitor voltage. the sampling circuit stores the boost voltage while the v sw is high and the linear regulator output transistor is reversed biased. vin 8.9 v bst vsw lsdr figure 37. boost circuit switch sampling circuit
ncp3155a, ncp3155b http://onsemi.com 15 reduced sampling time occurs at high duty cycles where the low side mosfet is of f for the majority of the switching period. reduced sampling time causes errors in the regulated voltage on the boost pin. high duty cycle / input voltage induced sampling errors can result in increased boost ripple voltage or higher than desired dc boost voltage. figure 38 outlines all operating regions. the recommended operating conditions are shown in region 1 (green) where a 0.1 f, 25 v ceramic capacitor can be placed on the boost pin without causing damage to the device or mosfets. larger boost ripple voltage occurring over several switching cycles is shown in region 2 (y ellow). the boost ripple frequency is dependent on the output capacitance selected. the ripple voltage will not damage the device or 12 v gate rated mosfets. conditions where maximum boost ripple voltage could damage the device or 12 v gate rated mosfets can be seen in region 3 (orange). placing a boost capacitor that is no greater than 3.3 nf on the boost pin limits the maximum boost voltage < 12 v. the typical drive waveforms for regions 1, 2 and 3 (green, yellow, and orange) regions of figure 38 are shown in figure 39. figure 38. safe operating area for boost voltage with a 0.1 f capacitor 5 1015202530354045505560657075808590 2 11.5v 22v 4 6 8 10 12 14 16 18 20 22 24 normal operation (region 1) increased boost ripple (still in specification) (region 2) increased boost ripple capacitor optimization required (region 3) 71% max duty cycle region 1 region 2 region 3 input voltage duty cycle boost voltage levels
ncp3155a, ncp3155b http://onsemi.com 16 vboost vin 7.5v normal maximum vboost vin normal maximum 0v vboost vin 7.5v figure 39. typical waveforms for region 1 (top), region 2 (middle), and region 3 (bottom) 7.5v 7.5v 7.5v 0v 7.5v 0v to illustrate, a 0.1 f boost capacitor operating at > 80% duty cycle and > 22.5 v input voltage will exceed the specifications for the driver supply voltage. see figure 40.
ncp3155a, ncp3155b http://onsemi.com 17 boost voltage 0 2 4 6 8 10 12 14 16 18 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26.5 input voltage (v) boost voltage (v) figure 40. boost voltage at 80% duty cycle voltage ripple maximum allowable voltage maximum boost voltage inductor selection when selecting the inductor, it is important to know the input and output requirements. some example conditions are listed below to assist in the process. table 1. design parameters design parameter example value input voltage (v in ) 9 v to 16 v nominal input voltage (v in ) 12 v output voltage (v out ) 3.3 v input ripple voltage (vin ripple ) 300 mv output ripple voltage (vout ripple ) 50 mv output current rating (i out ) 3 a operating frequency (fsw) 500 khz a buck converter produces input voltage (v in ) pulses that are lc filtered to produce a lower dc output voltage (v out ). the output voltage can be changed by modifying the on time relative to the switching period (t) or switching frequency. the ratio of high side switch on time to the switching period is called duty cycle (d). duty cycle can also be calculated using v out , v in , the low side switch voltage drop v lsd , and the high side switch voltage drop v hsd . f 1 t (eq. 3) d t on t ( d t off t (eq. 4) d v out
v lsd v in v hsd
v lsd d v out v in (eq. 5) 27.5% 3.3 v 12 v the ratio of ripple current to maximum output current simplifies the equations used for inductor selection. the formula for this is given in equation 6. ra i i out (eq. 6) the designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between 10% and 40%. when using ceramic output capacitors the ripple current can be greater thus a user might select a higher ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. now, acceptable values of inductance for a design can be calculated using equation 7. l v out i out ra f sw ( 1 d ) 8.2 h (eq. 7) 3.3 v 3a 20% 500 khz ( 1 27.5% ) the relationship between ra and l for this design example is shown in figure 41.
ncp3155a, ncp3155b http://onsemi.com 18 0 2 4 6 8 10 12 14 16 18 20 10% 15% 20% 25% 30% 35% 40% v in , (v) l, inductance ( h) 18 v ? in v out = 3.3 v figure 41. ripple current ratio vs. inductance 12 v ? in 9 v ? in to keep within the bounds of the parts maximum rating, calculate the rms current and peak current. i rms i out 1
ra 2 12 3.01 a (eq. 8) 3a 1
(0.2) 2 12 i pk i out 1
ra 2 3.3 a 3a 1
(0.2) 2 (eq. 9) an inductor for this example would be around 8.2 h and should support an rms current of 3.01 a and a peak current of 3.3 a. the final selection of an output inductor has both mechanical and electrical considerations. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the lar gest components in the regulation system, a minimum inductor value is particularly important in space ? constrained applications. from an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by equation 10. slewrate lout v in v out l out 1.1 a s (eq. 10) 12 v 3.3 v 8.2 h this equation implies that larger inductor values limit the regulator?s ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. this results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. the peak ? to ? peak ripple current for the ncp3155a is given by the following equation: i pp v out ( 1 d ) l out f sw (eq. 11) ipp is the peak to peak current of the inductor. from this equation it is clear that the ripple current increases as l out decreases, emphasizing the trade ? off between dynamic response and ripple current. the power dissipation of an inductor consists of both copper and core losses. the copper losses can be further categorized into dc losses and ac losses. a good first order approximation of the inductor losses can be made using the dc resistance as they usually contribute to 90% of the losses of the inductor shown below: lp cu i rms 2 dcr (eq. 12) the core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. most vendors will provide the appropriate information to make accurate calculations of the power dissipation then the total inductor losses can be capture buy the equation below: lp tot lp cu_dc
lp cu_ac
lp core (eq. 13) input capacitor selection the input capacitor has to sustain the ripple current produced during the on time of the upper mosfet, so it must have a low esr to minimize the losses. the rms value of this ripple is: iin rms i out d ( 1 d ) (eq. 14) d is the duty cycle, iin rms is the input rms current, and i out is the load current. the equation reaches its maximum value with d = 0.5. loss in the input capacitors can be calculated with the following equation: p cin esr cin i in rms 2 (eq. 15) p cin is the power loss in the input capacitors and esr cin is the effective series resistance of the input capacitance. due to large di/dt through the input capacitors, electrolytic or ceramics should be used. if a tantalum must be used, it must by surge protected. otherwise, capacitor failure could occur. input start ? up current to calculate the input startup current, the following equation can be used. i inrush c out v out t ss (eq. 16) i inrush is the input current during startup, c out is the total output capacitance, v out is the desired output voltage, and t ss is the soft start interval. if the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used.
ncp3155a, ncp3155b http://onsemi.com 19 output capacitor selection the important factors to consider when selecting an output capacitor is dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. the output capacitor must be rated to handle the ripple current at full load with proper derating. the rms ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies but a multiplier is usually given for higher frequency operation. the rms current for the output capacitor can be calculated below: co rms i o ra 12 (eq. 17) the maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (esl) and esr. the main component of the ripple voltage is usually due to the esr of the output capacitor and the capacitance selected. v esr_c i o ra esr co
1 8 f sw co (eq. 18) the esl of capacitors depends on the technology chosen but tends to range from 1 nh to 20 nh where ceramic capacitors have the lowest inductance and electrolytic capacitors then to have the highest. the calculated contributing voltage ripple from esl is shown for the switch on and switch off below: v eslon esl i pp f sw d (eq. 19) v esloff esl i pp f sw ( 1 d ) (eq. 20) the output capacitor is a basic component for the fast response of the power supply. in fact, during load transient, for the first few microseconds it supplies the current to the load. the controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. during a load step transient the output voltage initially drops due to the current variation inside the capacitor and the esr (neglecting the effect of the effective series inductance (esl)). v out ? esr i tran esr co (eq. 21) a minimum capacitor value is required to sustain the current during the load transient without discharging it. the voltage drop due to output capacitor discharge is approximated by the following equation: v out ? dischg i tran 2 l out c out v in v out (eq. 22) in a typical converter design, the esr of the output capacitor bank dominates the transient response. it should be noted that vout ? discharge and vout ? esr are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the esl). conversely during a load release, the output voltage can increase as the energy stored in the inductor dumps into the output capacitor. the esr contribution from equation 18 still applies in addition to the output capacitor charge which is approximated by the following equation: v out ? chg i tran 2 l out c out v out (eq. 23) as with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations. feedback and compensation the ncp3155 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. compensation is needed to achieve accurate output voltage regulation and fast transient response. the goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45 ). the transfer function of the power stage (the output lc filter) is a double pole system. the resonance frequency of this filter is expressed as follows: f p0 1 2 l c out (eq. 24) parasitic equivalent series resistance (esr) of the output filter capacitor introduces a high frequency zero to the filter network. its value can be calculated by using the following equation: f z0 1 2 c out esr (eq. 25) the main loop zero crossover frequency f 0 can be chosen to be 1/10 ? 1/5 of the switching frequency. table 2 shows the three methods of compensation. table 2. compensation types zero crossover frequency condition compensation type typical output capacitor type f p0 < f z0 < f 0 < f s /2 type ii electrolytic, tantalum f p0 < f 0 < f z0 < f s /2 type iii method i tantalum, ceramic f p0 < f 0 < f s /2 < f z0 type iii method ii ceramic
ncp3155a, ncp3155b http://onsemi.com 20 compensation type ii this compensation is suitable for electrolytic capacitors. components of the type ii (figure 42) network can be specified by the following equations: figure 42. type ii compensation r c1 2 f 0 l v ramp v out esr v in v ref gm (eq. 26) c c1 1 0.75 2 f p0 r c1 (eq. 27) c c2 1 r c1 f s (eq. 28) r1 v out v ref v ref r2 (eq. 29) v ramp is the peak ? to ? peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. capacitor c c2 is optional. compensation type iii tantalum and ceramics capacitors have lower esr than electrolytic, so the zero of the output lc filter goes to a higher frequency above the zero crossover frequency. this requires a type iii compensation network as shown in figure 43. there are two methods to select the zeros and poles of this compensation network. method i is ideal for tantalum output capacitors, which have a higher esr than ceramic: figure 43. type iii compensation f z1 0.75 f p0 (eq. 30) f z2 f p0 (eq. 31) f p2 f z0 (eq. 32) f p3 f s 2 (eq. 33) method ii is better suited for ceramic capacitors that typically have the lowest esr available: f z2 f 0 1 sin max 1
sin max (eq. 34) f p2 f 0 1
sin max 1 sin max (eq. 35) f z1 0.5 f z2 (eq. 36) f p3 0.5 f s (eq. 37) max is the desired maximum phase margin at the zero crossover frequency, ? 0 . it should be 45 ? 75 . convert degrees to radians by the formula: max max degress 2 360 :units radians (eq. 38) the remaining calculations are the same for both methods. r c1 2 gm (eq. 39) c c1 1 2 f z1 r c1 (eq. 40) c c2 1 2 f p3 r c1 (eq. 41) c fb1 2 f 0 l v ramp c out v in r c1 (eq. 42) r fb1 1 2 c fb1 f p2 (eq. 43) r1 1 2 c fb1 f z2 r fb1 (eq. 44) r2 v ref v out v ref r1 (eq. 45) if the equation in equation 46 is not true, then a higher value of r c1 must be selected. r1 r2 r fb1 r1 r fb1
r2 r fb1
r1 r2 1 gm (eq. 46)
ncp3155a, ncp3155b http://onsemi.com 21 output current derating the ncp3155 has a wide input voltage and output voltage capability. it also operates in a variety of thermal environments. these thermal conditions limit the maximum output current for a given input and output voltage. therefore, proper output current derating must be considered, taking into account ambient temperature, airflow, the input and output conditions, and the need for increased reliability. figures 24 ? 29 show safe operating conditions vs. output current for input voltages of 12 v, 18 v, and 24 v. these curves assumed 300 mm 2 of 2 oz copper. sufficient cooling could also be provided to ensure reliable operation. finally, to maintain operation in the safe operating areas shown in the curves, it is recommended to use the ncp3155 with input to output conditions as shown in figure 44. figure 44. recommended maximum output voltage vs input voltage 0 2 4 6 8 10 12 14 4 6 8 1012141618202224 v in , input voltage (v) v out , output voltage (v)
ncp3155a, ncp3155b http://onsemi.com 22 ncp3155a fb1 vout bst vsw pgnd agnd iset comp vin vin 5 v 10.8 ? 24 v 0.1 8.2 150 22 47 47 24k 33p 1.8n 18.2k r1 19.62k 649 820p figure 45. typical application circuit figure 46. typical application circuit 680p 1.5 vout (v) r1 (k ) 1.2 39.2k 1.5 22.1k 3.3 6.19k 5.0 3.74k ncp3155b fb1 vout bst vsw pgnd agnd iset comp vin vin 1.8 v 9 ? 16 v 0.1 4.7 150 22 220 220 22.1k 220p 12n 4.7k 4.99k 6.21k 649 2.2n 680p 1.5
ncp3155a, ncp3155b http://onsemi.com 23 figure 47. typical application circuit figure 48. typical application circuit ncp3155b fb1 vout bst vsw pgnd agnd iset comp vin vin 3.3 v 10.8 ? 14 v 0.1 4.7 150 22 22 22 24k 10p 1.2n 27k 6.19k 19.62k 270 560p 680p 1.5 ncp3155b fb1 vout bst vsw pgnd agnd iset comp vin vin 3.3 v 10 ? 14 v 0.1 4.7 150 22 10 220 22.1k 150p 8.2n 6.8k 4.99k 15.8k 580 680p 680p 1.5
ncp3155a, ncp3155b http://onsemi.com 24 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp3155/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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